1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a write controller for carrying out write control of a memory cell.
2. Description of the Related Art
Among non-volatile semiconductor memories, a NAND flash memory is known for its capability to cope with an increasing memory capacity and high integration. In a chip of the NAND flash memory, a plurality of NAND memory cells (hereinafter referred to as NAND cells) is arranged in a cell array area. Each of the NAND cells includes a plurality of memory cell transistors each having a stacked gate structure constituted of a floating gate and control gate, and connected in series, and select transistors connected to both ends of the plurality of memory cell transistors.
When data is written to the NAND cell, a system for carrying out control in such a manner that a program operation and a verification operation are alternately repeated is used in order to narrow the distribution width of the threshold voltage of the memory cell transistors. A plurality of the program operations and a plurality of the verifications operation are collectively called a write operation in some cases. In this case, the program operation is carried out in several times while the program voltage (Vpgm) is gradually stepped up. That is, the program operation is carried out while the program voltage (Vpgm) is stepped up, and the verification operation is carried out after each program operation. The verification operation implies an operation for confirming whether or not the threshold voltage of the memory cell transistor could have been written (increased) to a target value. In this case, if the target value is not attained, the program operation and the verification operation are carried out again. On the other hand, if it is determined that the program has been carried out to the target value, a voltage close to the power supply voltage is applied to a bit line BL connected to the NAND cell at the time of the next program, and the channel of the memory cell transistor is brought into a boosted state in order that the memory cell transistor in the unselected state can be prevented from being additionally programmed.
It should be noted that normally, in order to allow a program margin to the NAND cell, the reference level (verification level) for judging the read data at the time of the verification operation is set at a voltage higher than the judgment reference level at the time of a normal read operation to a certain degree.
However, due to the variation of the process and the circuit, the amount of change in the threshold voltage of the memory cell transistor becomes non-proportional with respect to a step-up in the program voltage (dVpgm), and the write operation may be terminated at a value lower than the target value in some cases. As a result of this, it becomes impossible to keep the threshold voltage within the target threshold voltage distribution width, and thus the reliability and performance are deteriorated. If it is intended to allow a margin for the lowering of the threshold voltage due to the above variation, the write operation must be carried out until a higher threshold voltage is obtained, leading to the other problem such as lowering of the yield.
It should be noted in U.S. Pat. No. 6,643,188, Tanaka et al., it is disclosed that a verification circuit for confirming the state of the memory cell after a write operation, and a data update circuit for updating the contents of a write data circuit to carry out rewrite to a memory cell insufficiently written on the basis of the contents of the write data circuit, and state of the memory cell after the write operation are provided, and the write operation based on the contents of the write data circuit, a write verification operation, and update of the contents of the write data circuit are repeated until the memory cell is brought into a predetermined written state.